An Improved Screen Method of Chip Selection for Suppressing Current Imbalance Between Paralleled Devices

In high-power applications, connecting SiC MOSFETs in parallel is a common practice that can effectively reduce conduction loss and increase current handling capability. However, the tolerances of MOSFETs can significantly impact their performance and reliability. This paper presents a novel screening method for selecting devices with closely matched parameters using static characterization to achieve matching dynamic performance. It mitigates the quantisation of curves as a source of interference by changing the computational range and optimises the selection algorithm. Dynamic and static test results based on 30 SiC MOSFETs show that the method used in this paper can select closed matched MOSFETs for parallel connections.