posted on 2021-08-23, 07:58authored byZhaonan Dong, Emmanuil H Georgoulis, Thomas Kappas
Discontinuous Galerkin (dG) methods on meshes consisting of polygonal/polyhedral
(henceforth, collectively termed as polytopic) elements have received considerable attention in recent
years. Due to the physical frame basis functions used typically and the quadrature challenges involved, the matrix-assembly step for these methods is often computationally cumbersome. To address
this important practical issue, this work proposes two parallel assembly implementation algorithms
on Compute Unified Device Architecture--enabled graphics cards for the interior penalty dG method
on polytopic meshes for various classes of linear PDE problems. We are concerned with both single
graphics processing unit (GPU) parallelization, as well as with implementation on distributed GPU
nodes. The results included showcase almost linear scalability of the quadrature step with respect to
the number of GPU cores used since no communication is needed for the assembly step. In turn, this
can justify the claim that polytopic dG methods can be implemented extremely efficiently, as any
assembly computing time overhead compared to finite elements on ``standard"" simplicial or box-type
meshes can be effectively circumvented by the proposed algorithms.
Funding
The Leverhulme Trust through grant RPG-2015- 306, and by Hellenic Foundation for Research and Innovation (H.F.R.I.) under the ``First Call for H.F.R.I. Research Projects to support Faculty members and Researchers and the procurement of high-cost research equipment grant"" (project 3270).
History
Citation
SIAM J. Sci. Comput., 43(4), C312–C334.
Author affiliation
School of Mathematics & Actuarial Science
Version
VoR (Version of Record)
Published in
SIAM Journal on Scientific Computing
Volume
43
Issue
4
Pagination
C312 - C334
Publisher
Society for Industrial & Applied Mathematics (SIAM)