Design and evaluation of a predictable embedded processor for use in timetriggered applications
thesisposted on 2015-07-07, 13:25 authored by Zemian Hughes
Embedded processors play a key role in many safety-critical applications including medical, automotive and aerospace systems. In such systems an inability to provide guarantees that the design will meet its requirements can have catastrophic consequences. To ensure that guarantees can be made, it must be possible to predict both the functional and temporal properties of the system at design time. The trend in modern embedded system design is currently leading towards unpredictable processor architectures in order to achieve increased performance. This trend presents fundamental challenges for the designers of timing analysis tools who are finding the accuracy and safety of timing estimations produced by new tools are getting worse. The consequence of this is that it is increasingly becoming harder to provide guarantees that the system requirements will be met. The primary causal factor is put down to the developments in modern processor architecture. This thesis attempts to address these problems with a novel, highly predictable embedded processor design for systems with a “time-triggered” (TT) system architecture. Even with a predictable processor, a real-time operating system (RTOS) implemented in software can itself complicate the temporal predictability of the system. To address this issue a predictable hardware TT scheduler is implemented in hardware. In order to overcome the possibility of the application programmer writing temporally unpredictable code, a set of software-based error-detection (and recovery) mechanisms is implemented as a “task guardian” to deal with issues of task overruns in TT systems. The performance and complexity of the initial software implementation leads to an innovative hardware task guardian solution. Overall, the implication of the studies presented in this thesis provide the system developer with an effective set of software and hardware components which are shown to provide a highly-predictable platform for the execution of time-triggered tasks sets.
Supervisor(s)Pont, Michael J.
Date of award2010-07-07
Author affiliationDepartment of Computer Science
Awarding institutionUniversity of Leicester